FPGA Development and Evaluation Board
Indian Space Research Organization · Kerala · Electronics & Instrumentation · open
Key facts
- Published: 10 Aug 2026
- Closing date: 24 Aug 2026
- Status: open
- Ministry: Department of Space
- Department: Department of Space
- Office: Iist Kerala
Description
Tender for the procurement of FPGA Development and Evaluation Boards, including specifications for processors, memory, connectivity, and peripherals, with a total quantity of 2 units, under the Department of Space, ISRO, Kerala office.
Eligibility & requirements
- Startup relaxation: No
- MSE relaxation: No
- Documents required: Certificate (Requested in ATC), OEM Authorization Certificate, Additional Document 1 (Requested in ATC), Compliance of BoQ specification and supporting document
New to these terms? Read how tender eligibility criteria work.
Commercial terms
- Bid type: Single Packet Bid
- Evaluation: value wise evaluation
- Make in India (MII): No
- MSE preference: Yes
Line items (1)
- FPGA Development and Evaluation Board — Qty: 2 pieces
1 tender document(s) available — sign up to download.
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