FPGA Development and Evaluation Board
Indian Institute of Technology (IIT) · West Bengal · Electronics & Instrumentation · open
Key facts
- Tender value: ₹2.3L
- Closing date: 21 Oct 2026
- Status: open
- Status as of: 01 Oct 2026 00:42 UTC
- Ministry: Ministry of Education
- Department: Department of Higher Education
- Office: Eastern Zone
Description
Tender for the supply of FPGA Development and Evaluation Board with specified technical parameters, including processor, memory, programmable logic, DSP slices, and warranty, for the Indian Institute of Technology (IIT) Kharagpur under the Department of Higher Education, Ministry of Education. The bid includes conditions for quantity variation, technical evaluation, and preference policies for MII and MSE bidders.
Eligibility & requirements
- Experience required: 0 years
- Past performance: 40%
- Startup relaxation: Yes
- MSE relaxation: Yes
- Documents required: BoQ specification, Supporting documents from seller, OEM Authorization Letter, University Program Authorization Letter
New to these terms? Read how tender eligibility criteria work.
Commercial terms
- Bid type: Two Packet Bid
- Evaluation: value wise evaluation
- Make in India (MII): Yes
- MSE preference: Yes
Line items (1)
- FPGA Development and Evaluation Board — Qty: 1 piece
1 tender document(s) available — sign up to download.
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