FPGA Development and Evaluation Board
Indian Space Research Organization · Sriharikota, Andhra Pradesh · Electronics & Instrumentation · open
Key facts
- Published: 18 Aug 2026
- Closing date: 08 Sep 2026
- Status: open
- Ministry: Department of Space
- Department: Department of Space
- Office: Satish Dhawan Space Centre SHAR
Description
Tender for the supply of FPGA Development and Evaluation Boards, including specifications for processors, memory, programmable logic, and additional parameters, with relaxation provisions for MSE and startups, and a bid validity of 90 days.
Eligibility & requirements
- Startup relaxation: Yes
- MSE relaxation: Yes
- Documents required: Experience/Turnover exemption documents, Udyam Certificate, Startup registration
New to these terms? Read how tender eligibility criteria work.
Commercial terms
- Bid type: Single Packet Bid
- Evaluation: value wise evaluation
- Make in India (MII): No
- MSE preference: Yes
Line items (1)
- FPGA Development and Evaluation Board — Qty: 4 pieces
1 tender document(s) available — sign up to download.
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