formalISA® Verification IP for C-DAC VEGA Processor variants ET1037, AT1051 and AS1061 Verification
Centre for Development of Advanced Computing (C-DAC) · Thiruvananthapuram, Kerala · Electronics & Instrumentation · open
Key facts
- Published: 25 Sep 2026
- Closing date: 16 Oct 2026
- Status: open
- Ministry: Ministry of Electronics and Information Technology
- Department: Department of Electronics and Information Technology
- Office: Thiruvananthapuram
Description
Tender for the supply of one set of formalISA® Verification IP for C-DAC VEGA Processor variants ET1037, AT1051, and AS1061 Verification, including technical specifications, bid validity, and eligibility criteria. The tender includes MII and MSE preferences, bid splitting, and delivery terms.
Eligibility & requirements
- Startup relaxation: Yes
- MSE relaxation: Yes
- Documents required: Turnover Criteria, Turnover Certificate, Udyam Certificate
New to these terms? Read how tender eligibility criteria work.
Commercial terms
- Bid type: Two Packet Bid
- Evaluation: value wise evaluation
- Make in India (MII): Yes
- MSE preference: Yes
Line items (1)
- formalISA® Verification IP for C-DAC VEGA Processor — Qty: 1 set
1 tender document(s) available — sign up to download.
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