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Design, Planning, Implementation, Integration, and Verification of Four 100G Ethernet IP Blocks on Stratix 10 RXPU FPGA for Synchronized Multi-Slice Band 4.5a. 5b Data Transfer

NCRA (Pune) - TIFR-DAE · Pune · Electronics & Instrumentation · open

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Description

Tender for designing, planning, implementing, integrating, and verifying four 100G Ethernet IP blocks on Stratix 10 RXPU FPGA to support synchronized multi-slice data transfer, building upon existing architecture, with a completion period of 12 months plus 6 months support, including EMD and performance guarantees.

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