Design, Planning, Implementation, Integration, and Verification of Four 100G Ethernet IP Blocks on Stratix 10 RXPU FPGA for Synchronized Multi-Slice Band 4.5a. 5b Data Transfer
NCRA (Pune) - TIFR-DAE · Pune · Electronics & Instrumentation · open
Key facts
- EMD: ₹1.8L
- Published: 31 Jul 2026
- Closing date: 14 Aug 2026
- Status: open
- Ministry: Department of Atomic Energy
- Department: Tata Institute of Fundamental Research
Description
Tender for designing, planning, implementing, integrating, and verifying four 100G Ethernet IP blocks on Stratix 10 RXPU FPGA to support synchronized multi-slice data transfer, building upon existing architecture, with a completion period of 12 months plus 6 months support, including EMD and performance guarantees.
Eligibility & requirements
- Startup relaxation: No
- MSE relaxation: No
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Commercial terms
- Bid type: Single
- Make in India (MII): No
- MSE preference: No
Line items (1)
- Ethernet IP Blocks on FPGA — Qty: 4 set
2 tender document(s) available — sign up to download.
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