10 Tap High Performance Passive Delay Line Chips
Directorate of Purchase and Stores · Mumbai, Maharashtra · Electronics & Instrumentation · open
Key facts
- Published: 03 Nov 2026
- Closing date: 27 Nov 2026
- Status: open
- Status as of: 05 Nov 2026 02:28 UTC
- Ministry: Department of Atomic Energy
- Department: Department of Atomic Energy
- Office: Directorate of Purchase and Stores
Description
Supply of 500 10 Tap High Performance Passive Delay Line Chips to the Material Receipt Cell, BARC, Trombay, Mumbai. Delivery period is 90 days. EMD is not required; ePBG of 5% is required for 5 months. Reverse auction is enabled with H1-Highest Priced Bid Elimination.
Eligibility & requirements
- Startup relaxation: Yes
- MSE relaxation: Yes
- Documents required: Certificate (Requested in ATC), Supporting documents to prove eligibility for exemption from experience or turnover criteria, Documents clearly specifying acceptance of all technical specifications, additional specification parameters and terms & conditions, on bidder's letterhead
New to these terms? Read how tender eligibility criteria work.
Commercial terms
- Bid type: Two Packet Bid
- Evaluation: Total value wise evaluation
- Make in India (MII): No
- MSE preference: Yes
Line items (1)
- 10 Tap High Performance Passive Delay Line Chips — Qty: 500 pieces
1 tender document(s) available — sign up to download.
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